PIC18F44J50-I Datasheet, PDF (125/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
REGISTER 9-9: PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h)
R/W-0
SSP2IE
bit 7
R/W-0
BCL2IE
R/W-0
RC2IE
R/W-0
TX2IE
R/W-0
TMR4IE
R/W-0
CTMUIE
R/W-0
TMR3GIE
R/W-0
RTCCIE
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module)
1 = Enabled
0 = Disabled
bit 5
RC2IE: EUSART2 Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TX2IE: EUSART2 Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
TMR4IE: TMR4 to PR4 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR3GIE: Timer3 Gate Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
RTCCIE: RTCC Interrupt Enable bit
1 = Enabled
0 = Disabled
 2011 Microchip Technology Inc.
DS39931D-page 125