PIC18F44J50-I Datasheet, PDF(73/562 Page) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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PIC18F44J50-I Datasheet, PDF (73/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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PIC18F46J50 FAMILY

TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable Devices

Power-on Reset,

Brown-out Reset,

Wake From Deep

Sleep

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

CM Resets

Wake-up via WDT

or Interrupt

BAUDCON1 PIC18F2XJ50 PIC18F4XJ50

0100 0-00

0100 0-00

uuuu u-uu

SPBRGH2

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

BAUDCON2 PIC18F2XJ50 PIC18F4XJ50

0100 0-00

0100 0-00

uuuu u-uu

TMR3H

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

TMR3L

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

T3CON

PIC18F2XJ50 PIC18F4XJ50

0000 0000

uuuu uuuu

uuuu uuuu

TMR4

PIC18F2XJ50 PIC18F4XJ50

0000 0000

uuuu uuuu

uuuu uuuu

PR4

PIC18F2XJ50 PIC18F4XJ50

1111 1111

1111 1111

uuuu uuuu

T4CON

PIC18F2XJ50 PIC18F4XJ50

-000 0000

-000 0000

-uuu uuuu

SSP2BUF

PIC18F2XJ50 PIC18F4XJ50

xxxx xxxx

uuuu uuuu

uuuu uuuu

SSP2ADD

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

SSP2MSK

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

SSP2STAT

PIC18F2XJ50 PIC18F4XJ50

1111 1111

1111 1111

uuuu uuuu

SSP2CON1 PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

SSP2CON2 PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

CMSTAT

PIC18F2XJ50 PIC18F4XJ50

---- --11

---- --11

---- --uu

PMADDRH(5)

â

PIC18F4XJ50

-000 0000

-000 0000

-uuu uuuu

PMDOUT1H(5)

â

PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

PMADDRL(5)

â

PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

PMDOUT1L(5)

â

PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

PMDIN1H(5)

â

PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

PMDIN1L(5)

â

PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

TXADDRL

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

TXADDRH

PIC18F2XJ50 PIC18F4XJ50

---- 0000

---- 0000

---- uuuu

RXADDRL

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

RXADDRH

PIC18F2XJ50 PIC18F4XJ50

---- 0000

---- 0000

---- uuuu

DMABCL

PIC18F2XJ50 PIC18F4XJ50

0000 0000

0000 0000

uuuu uuuu

DMABCH

PIC18F2XJ50 PIC18F4XJ50

---- --00

---- --00

---- --uu

UCON

PIC18F2XJ50 PIC18F4XJ50

-0x0 000-

-0x0 000-

-uuu uuu-

USTAT

PIC18F2XJ50 PIC18F4XJ50

-xxx xxx-

-xxx xxx-

-uuu uuu-

UEIR

PIC18F2XJ50 PIC18F4XJ50

0--0 0000

0--0 0000

u--u uuuu

UIR

PIC18F2XJ50 PIC18F4XJ50

-000 0000

-000 0000

-uuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as â0â, q = value depends on condition.

Note 1: When the wake-up is due to an interrupt and the GIEH (and GIEL if low priority) bit(s) are set, the TOSU,

TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the

next location in the hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

4: See Table 5-1 for Reset value for specific condition.

5: Not implemented on PIC18F2XJ50 devices.

6: Not implemented on âLFâ devices.

ï£ 2011 Microchip Technology Inc.

DS39931D-page 73

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