PIC18F44J50-I Datasheet, PDF (266/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
FIGURE 18-18:
STRA
PxA Signal
CCPxM1
PORT Data
STRB
SIMPLIFIED STEERING
BLOCK DIAGRAM
RPn Pin
1
0
TRIS
CCPxM0
PORT Data
STRC
1
RPn Pin
0
TRIS
CCPxM1
PORT Data
STRD
1
RPn Pin
0
TRIS
CCPxM0
1
RPn Pin
PORT Data
0
TRIS
Note 1:
2:
Port outputs are configured as displayed
when the CCPxCON register bits,
PxM<1:0> = 00 and CCPxM<3:2> = 11.
Single PWM output requires setting at least
one of the STRx bits.
18.5.7.1 Steering Synchronization
The STRSYNC bit of the PSTRxCON register gives the
user two selections of when the steering event will
happen. When the STRSYNC bit is ‘0’, the steering
event will happen at the end of the instruction that
writes to the PSTRxCON register. In this case, the out-
put signal at the Px<D:A> pins may be an incomplete
PWM waveform. This operation is useful when the user
firmware needs to immediately remove a PWM signal
from the pin.
When the STRSYNC bit is ‘1’, the effective steering
update will happen at the beginning of the next PWM
period. In this case, steering on/off the PWM output will
always produce a complete PWM waveform.
Figures 18-19 and 18-20 illustrate the timing diagrams
of the PWM steering depending on the STRSYNC
setting.
FIGURE 18-19:
PWM
STRn
EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0)
PWM Period
P1<D:A>
Port Data
P1n = PWM
Port Data
FIGURE 18-20: EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1)
PWM
STRn
P1<D:A>
Port Data
P1n = PWM
Port Data
DS39931D-page 266
 2011 Microchip Technology Inc.