PIC18F44J50-I Datasheet, PDF (350/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
The
analog
reference
voltage
is
software-selectable to either the device’s positive
and negative supply voltage (AVDD and AVSS), or
the voltage level on the RA3/AN3/VREF+/C1INB and
RA2/AN2/VREF-/CVREF/C2INB pins.
The A/D Converter has a unique feature of being able
to operate while the device is in Sleep mode. To
operate in Sleep, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via Successive
Approximation (SAR).
Each port pin associated with the A/D Converter can be
configured as an analog input or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH:ADRESL
register pair, the GO/DONE bit (ADCON0<1>) is
cleared and the A/D Interrupt Flag bit, ADIF, is set.
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted. The value in the
ADRESH:ADRESL register pair is not modified for a
Power-on Reset (POR). These registers will contain
unknown data after a POR.
Figure 21-1 provides the block diagram of the A/D
module.
FIGURE 21-1:
A/D BLOCK DIAGRAM
CHS<3:0>
1111
1110
1100
1011
1010
1001
1000
0111
10-Bit
A/D
Converter
VAIN
(Input Voltage)
0110
0101
0100
0011
0010
Reference
Voltage
VCFG<1:0>
VREF+
VREF-
VDD⁽²⁾
0001
0000
VSS⁽²⁾
Note 1: Channels, AN5, AN6 and AN7, are not available on 28-pin devices.
2: I/O pins have diode protection to VDD and VSS.
VBG
VDDCORE/VCAP
AN12
AN11
AN10
AN9
AN8
AN7⁽¹⁾
AN6⁽¹⁾
AN5⁽¹⁾
AN4
AN3
AN2
AN1
AN0
DS39931D-page 350
 2011 Microchip Technology Inc.