PIC18F44J50-I Datasheet, PDF (149/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 10-11: PORTE I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/AN5/
PMRD
RE0
1
I
ST PORTE<0> data input; disabled when analog input is
enabled.
0
O DIG LATE<0> data output; not affected by analog input.
AN5
1
I ANA A/D Input Channel 5; default input configuration on POR.
PMRD
1
I ST/TTL Parallel Master Port io_rd_in.
0
O DIG Parallel Master Port read strobe.
RE1/AN6/
PMWR
RE1
1
I
ST PORTE<1> data input; disabled when analog input is
enabled.
0
O DIG LATE<1> data output; not affected by analog input.
AN6
1
I ANA A/D Input Channel 6; default input configuration on POR.
PMWR
1
I ST/TTL Parallel Master Port io_wr_in.
0
O DIG Parallel Master Port write strobe.
RE2/AN7/
PMCS
RE2
1
I
ST PORTE<2> data input; disabled when analog input is
enabled.
0
O DIG LATE<2> data output; not affected by analog input.
AN7
1
I ANA A/D Input Channel 7; default input configuration on POR.
PMCS
0
O DIG Parallel Master Port byte enable.
Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level;
I = Input; O = Output; P = Power
TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PORTE⁽¹⁾
RDPU
REPU
—
—
—
RE2
LATE⁽¹⁾
—
—
—
—
—
LATE2
TRISE⁽¹⁾
—
—
—
—
—
TRISE2
ANCON0 PCFG7⁽²⁾ PCFG6⁽²⁾ PCFG5⁽²⁾ PCFG4 PCFG3 PCFG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1: These registers are not available on 28-pin devices.
2: These bits are only available on 44-pin devices.
RE1
LATE1
TRISE1
PCFG1
Bit 0
RE0
LATE0
TRISE0
PCFG0
Reset
Values
on Page
92
92
92
94
 2011 Microchip Technology Inc.
DS39931D-page 149