PIC18F44J50-I Datasheet, PDF (219/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
15.5.4
TIMER3 GATE SINGLE PULSE
MODE
When Timer3 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer3
Gate Single Pulse mode is first enabled by setting the
T3GSPM bit in the T3GCON register. Next, the
T3GGO/T3DONE bit in the T3GCON register must be
set.
The Timer3 will be fully enabled on the next increment-
ing edge. On the next trailing edge of the pulse, the
T3GGO/T3DONE bit will automatically be cleared. No
other gate events will be allowed to increment Timer3
until the T3GGO/T3DONE bit is once again set in
software.
Clearing the T3GSPM bit of the T3GCON register will
also clear the T3GGO/T3DONE bit. See Figure 15-4
for timing details.
Enabling the Toggle mode and the Single Pulse mode,
simultaneously, will permit both sections to work
together. This allows the cycle times on the Timer3 gate
source to be measured. See Figure 15-5 for timing
details.
FIGURE 15-4:
TIMER3 GATE SINGLE PULSE MODE
TMR3GE
T3GPOL
T3GSPM
T3GGO/
T3DONE
T3G_IN
Set by Software
Counting Enabled on
Rising Edge of T3G
Cleared by Hardware on
Falling Edge of T3GVAL
T1CKI
T3GVAL
Timer3
TMR3GIF
N
Cleared by Software
N+1
N+2
Set by Hardware on
Falling Edge of T3GVAL
Cleared by
Software
 2011 Microchip Technology Inc.
DS39931D-page 219