PIC18F44J50-I Datasheet, PDF (115/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
9.0 INTERRUPTS
Devices of the PIC18F46J50 family have multiple inter-
rupt sources and an interrupt priority feature that allows
most interrupt sources to be assigned a high-priority
level or a low-priority level. The high-priority interrupt
vector is at 0008h and the low-priority interrupt vector
is at 0018h. High-priority interrupt events will interrupt
any low-priority interrupts that may be in progress.
There are 13 registers, which are used to control
interrupt operation. These registers are:
• RCON
• INTCON
• INTCON2
• INTCON3
• PIR1, PIR2, PIR3
• PIE1, PIE2, PIE3
• IPR1, IPR2, IPR3
It is recommended that the Microchip header files
supplied with MPLAB^® IDE be used for the symbolic
bit names in these registers. This allows the
assembler/compiler to automatically take care of the
placement of these bits within the specified register.
In general, interrupt sources have three bits to control
their operation. They are:
• Flag bit to indicate that an interrupt event
occurred
• Enable bit that allows program execution to
branch to the interrupt vector address when the
flag bit is set
• Priority bit to select high priority or low priority
The interrupt priority feature is enabled by setting the
IPEN bit (RCON<7>). When interrupt priority is
enabled, there are two bits which enable interrupts
globally. Setting the GIEH bit (INTCON<7>) enables all
interrupts that have the priority bit set (high priority).
Setting the GIEH and GIEL bits (INTCON<7:6>)
enables interrupts that have the priority bit cleared (low
priority). When the interrupt flag, enable bit and
appropriate Global Interrupt Enable bits are set, the
interrupt will vector immediately to address, 0008h or
0018h, depending on the priority bit setting. Individual
interrupts can be disabled through their corresponding
enable bits.
When the IPEN bit is cleared (default state), the
interrupt priority feature is disabled and interrupts are
compatible with PIC^® mid-range devices. In
Compatibility mode, the interrupt priority bits for each
source have no effect. INTCON<6> is the PEIE bit,
which enables/disables all peripheral interrupt sources.
INTCON<7> is the GIE bit, which enables/disables all
interrupt sources. All interrupts branch to address,
0008h, in Compatibility mode.
When an interrupt is responded to, the Global Interrupt
Enable bit is automatically cleared by hardware to dis-
able further interrupts. If the IPEN bit is cleared, this is
the GIE bit. If interrupt priority levels are used, this will be
either the GIEH bit, if the interrupt was configured for
high-priority, or the GIEL bit, if the interrupt was config-
ured for low-priority. When executing in the interrupt
context, application firmware should not attempt to
manually re-enable the respective GIEH or GIEL bit that
was cleared in hardware. High-priority interrupt sources
can interrupt a low-priority interrupt. Low-priority inter-
rupts are not processed while high-priority interrupts are
in progress.
When an interrupt occurs, the return address is pushed
onto the stack and the PC is loaded with the interrupt
vector address (0008h or 0018h). Once in the Interrupt
Service Routine (ISR), the source(s) of the interrupt
can be determined by polling the interrupt flag bits. The
interrupt flag bit, or individual PIEx enable bit, must be
cleared in software before returning from the interrupt
handler to avoid recursive interrupts.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine and sets the GIE bit (GIEH or GIEL
if priority levels are used), which re-enables interrupts.
For external interrupt events, such as the INTx pins or
the PORTB input change interrupt, the interrupt latency
will be three to four instruction cycles. The exact
latency is the same for one or two-cycle instructions.
Individual interrupt flag bits are set regardless of the
status of their corresponding enable bit or the GIE bit.
Note:
Do not use the MOVFF instruction to modify
any of the interrupt control registers while
any interrupt is enabled. Doing so may
cause erratic microcontroller behavior.
 2011 Microchip Technology Inc.
DS39931D-page 115