PIC18F44J50-I Datasheet, PDF (217/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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15.3 Timer3 16-Bit Read/Write Mode
Timer3 can be configured for 16-bit reads and writes
(see Section 15.3 “Timer3 16-Bit Read/Write
Mode”). When the RD16 control bit (T3CON<1>) is
set, the address for TMR3H is mapped to a buffer reg-
ister for the high byte of Timer3. A read from TMR3L
will load the contents of the high byte of Timer3 into the
Timer3 High Byte Buffer register. This provides the user
with the ability to accurately read all 16 bits of Timer3
without having to determine whether a read of the high
byte, followed by a read of the low byte, has become
invalid due to a rollover between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
15.4 Using the Timer1 Oscillator as the
Timer3 Clock Source
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN (T1CON<3>) bit. To use it as the
Timer3 clock source, the TMR3CS bit must also be set.
As previously noted, this also configures Timer3 to
increment on every rising edge of the oscillator source.
The Timer1 oscillator is described in Section 13.0
“Timer1 Module”.
15.5 Timer3 Gate
Timer3 can be configured to count freely or the count
can be enabled and disabled using Timer3 gate
circuitry. This is also referred to as Timer3 gate count
enable.
Timer3 gate can also be driven by multiple selectable
sources.
15.5.1 TIMER3 GATE COUNT ENABLE
The Timer3 Gate Enable mode is enabled by setting
the TMR3GE bit of the T3GCON register. The polarity
of the Timer3 Gate Enable mode is configured using
the T3GPOL bit of the T3GCON register.
When Timer3 Gate Enable mode is enabled, Timer3
will increment on the rising edge of the Timer3 clock
source. When Timer3 Gate Enable mode is disabled,
no incrementing will occur and Timer3 will hold the
current count. See Figure 15-2 for timing details.
TABLE 15-1: TIMER3 GATE ENABLE
SELECTIONS
T3CLK T3GPOL T3G Timer3 Operation

0
0 Counts

0
1 Holds Count

1
0 Holds Count

1
1 Counts
FIGURE 15-2:
TMR3GE
TIMER3 GATE COUNT ENABLE MODE
T3GPOL
T3G_IN
T1CKI
T3GVAL
Timer3
N
N+1
N+2
N+3
N+4
 2011 Microchip Technology Inc.
DS39931D-page 217