PIC18F44J50-I Datasheet, PDF (338/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
69
PIR1
PMPIF⁽¹⁾ ADIF
RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF
72
PIE1
PMPIE⁽¹⁾ ADIE
RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE
72
IPR1
PMPIP⁽¹⁾ ADIP
RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP
72
PIR3
SSP2IF BCL2IF RC2IF TX2IF TMR4IF CTMUIF TMR3GIF RTCCIF
72
PIE3
SSP2IE BCL2IE RC2IE TX2IE TMR4IE CTMUIE TMR3GIE RTCCIE
72
IPR3
SSP2IP BCL2IP RC2IP TX2IP TMR4IP CTMUIP TMR3GIP RTCCIP
72
RCSTAx
SPEN
RX9
SREN CREN ADDEN FERR OERR RX9D
71
RCREGx EUSARTx Receive Register
71
TXSTAx
CSRC
TX9
TXEN SYNC SENDB BRGH TRMT TX9D
71
BAUDCONx ABDOVF RCIDL RXDTP TXCKP BRG16
—
WUE ABDEN
73
SPBRGHx EUSARTx Baud Rate Generator Register High Byte
71
SPBRGx EUSARTx Baud Rate Generator Register Low Byte
71
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1: These bits are only available on 44-pin devices.
20.2.3
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the BRG is inactive and a
proper byte reception cannot be performed. The
auto-wake-up feature allows the controller to wake-up
due to activity on the RXx/DTx line while the EUSART
is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the
LIN/J2602 support protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 20-8) and asynchronously if the device is in
Sleep mode (Figure 20-9). The interrupt condition is
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
20.2.3.1 Special Considerations Using
Auto-Wake-up
Since auto-wake-up functions by sensing rising edge
transitions on RXx/DTx, information with any state
changes before the Stop bit may signal a false
End-of-Character (EOC) and cause data or framing
errors. To work properly, therefore, the initial character
in the transmission must be all ‘0’s. This can be 00h
(8 bits) for standard RS-232 devices or 000h (12 bits)
for LIN/J2602 bus.
Oscillator start-up time must also be considered,
especially in applications using oscillators with
longer start-up intervals (i.e., HS or HSPLL mode).
The Sync Break (or Wake-up Signal) character must
be of sufficient length, and be followed by a sufficient
interval, to allow enough time for the selected
oscillator to start and provide proper initialization of
the EUSART.
DS39931D-page 338
 2011 Microchip Technology Inc.