PIC18F44J50-I Datasheet, PDF (209/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
13.8.4
TIMER1 GATE SINGLE PULSE
MODE
When Timer1 Gate Single Pulse mode is enabled, it is
possible to capture a single pulse gate event. Timer1
Gate Single Pulse mode is first enabled by setting the
T1GSPM bit in the T1GCON register. Next, the
T1GGO/T1DONE bit in the T1GCON register must be
set. The Timer1 will be fully enabled on the next incre-
menting edge. On the next trailing edge of the pulse,
the T1GGO/T1DONE bit will automatically be cleared.
No other gate events will be allowed to increment
Timer1 until the T1GGO/T1DONE bit is once again set
in software.
Clearing the T1GSPM bit of the T1GCON register will
also clear the T1GGO/T1DONE bit. See Figure 13-6
for timing details.
Enabling the Toggle mode and the Single Pulse mode,
simultaneously, will permit both sections to work together.
This allows the cycle times on the Timer1 gate source to
be measured. See Figure 13-7 for timing details.
13.8.5 TIMER1 GATE VALUE STATUS
When the Timer1 gate value status is utilized, it is
possible to read the most current level of the gate
control value. The value is stored in the T1GVAL bit in
the T1GCON register. The T1GVAL bit is valid even
when the Timer1 gate is not enabled (TMR1GE bit is
cleared).
FIGURE 13-6:
TIMER1 GATE SINGLE PULSE MODE
TMR1GE
T1GPOL
T1GSPM
T1GGO/
T1DONE
T1G_IN
Set by Software
Counting Enabled on
Rising Edge of T1G
Cleared by Hardware on
Falling Edge of T1GVAL
T1CKI
T1GVAL
Timer1
TMR1GIF
N
Cleared by Software
N+1
N+2
Set by Hardware on
Falling Edge of T1GVAL
Cleared by
Software
 2011 Microchip Technology Inc.
DS39931D-page 209