PIC18F44J50-I Datasheet, PDF (208/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
13.8.2
TIMER1 GATE SOURCE
SELECTION
The Timer1 gate source can be selected from one of
four different sources. Source selection is controlled by
the T1GSSx bits of the T1GCON register. The polarity
for each available source is also selectable. Polarity
selection is controlled by the T1GPOL bit of the
T1GCON register.
TABLE 13-4: TIMER1 GATE SOURCES
T1GSS<1:0>
Timer1 Gate Source
00
Timer1 Gate Pin
01
Overflow of Timer0
(TMR0 increments from FFh to 00h)
10
TMR2 to Match PR2
(TMR2 increments to match PR2)
13.8.2.1 T1G Pin Gate Operation
The T1G pin is one source for Timer1 gate control. It
can be used to supply an external source to the Timer1
gate circuitry.
13.8.2.2 Timer0 Overflow Gate Operation
When Timer0 increments from FFh to 00h, a
low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
FIGURE 13-5:
TMR1GE
T1GPOL
TIMER1 GATE TOGGLE MODE
13.8.2.3 Timer2 Match Gate Operation
The TMR2 register will increment until it matches the
value in the PR2 register. On the very next increment
cycle, TMR2 will be reset to 00h. When this Reset occurs,
a low-to-high pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
The pulse remains high for one instruction cycle and
returns to low until the next match.
When T1GPOL = 1, Timer1 increments for a single
instruction cycle, following TMR2 matching PR2.
With T1GPOL = 0, Timer1 increments, except during
the cycle following the match.
13.8.3 TIMER1 GATE TOGGLE MODE
When Timer1 Gate Toggle mode is enabled, it is
possible to measure the full cycle length of a Timer1 gate
signal, as opposed to the duration of a single level pulse.
The Timer1 gate source is routed through a flip-flop that
changes state on every incrementing edge of the
signal. See Figure 13-5 for timing details.
The T1GVAL bit will indicate when the Toggled mode is
active and the timer is counting.
The Timer1 Gate Toggle mode is enabled by setting the
T1GTM bit of the T1GCON register. When the T1GTM
bit is cleared, the flip-flop is cleared and held clear. This
is necessary in order to control which edge is
measured.
T1GTM
T1G_IN
T1CKI
T1GVAL
Timer1
N
N+1 N+2 N+3
N+4
N+5 N+6 N+7 N+8
DS39931D-page 208
 2011 Microchip Technology Inc.