PIC18F44J50-I Datasheet, PDF (556/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
SPI Clock ................................................................. 275
SSPxBUF Register .................................................. 275
SSPxSR Register ..................................................... 275
Typical Connection .................................................. 274
SSPOV ............................................................................. 313
SSPOV Status Flag .......................................................... 313
SSPxSTAT Register
R/W Bit ............................................................. 293, 296
SSx ................................................................................... 270
Stack Full/Underflow Resets .............................................. 81
SUBFSR ........................................................................... 481
SUBFWB .......................................................................... 470
SUBLW ............................................................................ 471
SUBULNK ........................................................................ 481
SUBWF ............................................................................ 471
SUBWFB .......................................................................... 472
SWAPF ............................................................................ 472
T
Table Pointer Operations (table) ...................................... 106
Table Reads/Table Writes .................................................. 81
TAD ................................................................................... 353
TBLRD ............................................................................. 473
TBLWT ............................................................................. 474
Timer0 .............................................................................. 195
Associated Registers ............................................... 197
Operation ................................................................. 196
Overflow Interrupt .................................................... 197
Prescaler .................................................................. 197
Switching Assignment ...................................... 197
Prescaler Assignment (PSA Bit) .............................. 197
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 197
Reads and Writes in 16-Bit Mode ............................ 196
Source Edge Select (T0SE Bit) ................................ 196
Source Select (T0CS Bit) ......................................... 196
Timer1 .............................................................................. 199
16-Bit Read/Write Mode ........................................... 205
Associated Registers ............................................... 210
Clock Source Selection ............................................ 203
Gate ......................................................................... 207
Interrupt .................................................................... 206
Operation ................................................................. 203
Oscillator .......................................................... 199, 205
Layout Considerations ..................................... 206
Resetting, Using the ECCP Special
Event Trigger ................................................... 207
TMR1H Register ...................................................... 199
TMR1L Register ....................................................... 199
Use as a Clock Source ............................................ 206
Timer2 .............................................................................. 211
Associated Registers ............................................... 212
Interrupt .................................................................... 212
Operation ................................................................. 211
Output ...................................................................... 212
Timer3 .............................................................................. 213
16-Bit Read/Write Mode ........................................... 217
Associated Registers ............................................... 221
Gate ......................................................................... 217
Operation ................................................................. 216
Oscillator .......................................................... 213, 217
Overflow Interrupt ............................................ 213, 221
Special Event Trigger (ECCP) ................................. 221
TMR3H Register ...................................................... 213
TMR3L Register ....................................................... 213
Timer4 .............................................................................. 223
Associated Registers ............................................... 224
Interrupt ................................................................... 224
MSSP Clock Shift .................................................... 224
Operation ................................................................. 223
Output ...................................................................... 224
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 223
Prescaler. See Prescaler, Timer4.
TMR4 Register ......................................................... 223
TMR4 to PR4 Match Interrupt .......................... 223, 224
Timing Diagrams
A/D Conversion ........................................................ 529
Asynchronous Reception ......................................... 337
Asynchronous Transmission .................................... 334
Asynchronous Transmission (Back-to-Back) ........... 334
Automatic Baud Rate Calculation ............................ 332
Auto-Wake-up Bit (WUE) During Normal
Operation ......................................................... 339
Auto-Wake-up Bit (WUE) During Sleep ................... 339
Baud Rate Generator with Clock Arbitration ............ 311
BRG Overflow Sequence ......................................... 332
BRG Reset Due to SDAx Arbitration During
Start Condition ................................................. 319
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 320
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 320
Bus Collision During a Start Condition
(SCLx = 0) ....................................................... 319
Bus Collision During a Stop Condition (Case 1) ...... 321
Bus Collision During a Stop Condition (Case 2) ...... 321
Bus Collision During Start Condition
(SDAx Only) ..................................................... 318
Bus Collision for Transmit and Acknowledge .......... 317
CLKO and I/O .......................................................... 512
Clock Synchronization ............................................. 304
Clock/Instruction Cycle .............................................. 82
Enhanced Capture/Compare/PWM ......................... 516
EUSARTx Synchronous Receive
(Master/Slave) ................................................. 528
EUSARTx Synchronous Transmission
(Master/Slave) ................................................. 528
Example SPI Master Mode (CKE = 0) ..................... 520
Example SPI Master Mode (CKE = 1) ..................... 521
Example SPI Slave Mode (CKE = 0) ....................... 522
Example SPI Slave Mode (CKE = 1) ....................... 523
External Clock .......................................................... 510
Fail-Safe Clock Monitor ........................................... 432
First Start Bit ............................................................ 311
Full-Bridge PWM Output .......................................... 258
Half-Bridge PWM Output ................................. 256, 263
High/Low-Voltage Detect Characteristics ................ 507
High-Voltage Detect (VDIRMAG = 1) ...................... 399
I²2C Bus Data .......................................................... 524
I²C Acknowledge Sequence .................................... 316
I²C Bus Start/Stop Bits ............................................ 524
I²C Master Mode (7 or 10-Bit Transmission) ........... 314
I²C Master Mode (7-Bit Reception) .......................... 315
I²C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001) ............................................ 300
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 301
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 306
I²C Slave Mode (10-Bit Transmission) .................... 302
DS39931D-page 556
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