PIC18F44J50-I Datasheet, PDF (49/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
On transitions from SEC_RUN mode to PRI_RUN
mode, the peripherals and CPU continue to be clocked
from the Timer1 oscillator while the primary clock is
started. When the primary clock becomes ready, a
clock switch back to the primary clock occurs (see
Figure 4-2). When the clock switch is complete, the
T1RUN bit is cleared, the OSTS bit is set and the
primary clock would be providing the clock. The IDLEN
and SCS bits are not affected by the wake-up; the
Timer1 oscillator continues to run.
FIGURE 4-1:
TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
T1OSI
OSC1
CPU
Clock
Peripheral
Clock
Program
Counter
Q1 Q2 Q3 Q4 Q1
1
PC
2
3
n-1 n
Clock Transition
PC + 2
Q2 Q3 Q4 Q1 Q2 Q3
PC + 4
FIGURE 4-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1
Q2
Q3
Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3
T1OSI
OSC1
PLL Clock
Output
CPU Clock
TOST⁽¹⁾
TPLL⁽¹⁾
1 2 n-1 n
Clock
Transition
Peripheral
Clock
Program
Counter
PC
PC + 2
SCS<1:0> Bits Changed
OSTS Bit Set
Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 4
 2011 Microchip Technology Inc.
DS39931D-page 49