PIC18F44J50-I Datasheet, PDF (260/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
FIGURE 18-13:
EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE
Forward Period
t1
Reverse Period
PxA
PxB
PxC
PxD
PW
External Switch C
External Switch D
Potential
Shoot-Through Current
PW
TON
TOFF
T = TOFF – TON
Note 1:
2:
3:
All signals are shown as active-high.
TON is the turn-on delay of power switch, QC, and its driver.
TOFF is the turn-off delay of power switch, QD, and its driver.
18.5.3 START-UP CONSIDERATIONS
When any PWM mode is used, the application
hardware must use the proper external pull-up and/or
pull-down resistors on the PWM output pins.
Note:
When the microcontroller is released from
Reset, all of the I/O pins are in the
high-impedance state. The external
circuits must keep the power switch
devices in the OFF state until the micro-
controller drives the I/O pins with the
proper signal levels or activates the PWM
output(s).
The CCPxM<1:0> bits of the CCPxCON register allow
the user to choose whether the PWM output signals are
active-high or active-low for each pair of PWM output
pins (PxA/PxC and PxB/PxD). The PWM output
polarities must be selected before the PWM pin output
drivers are enabled. Changing the polarity configura-
tion while the PWM pin output drivers are enable is not
recommended since it may result in damage to the
application circuits.
The PxA, PxB, PxC and PxD output latches may not be
in the proper states when the PWM module is
initialized. Enabling the PWM pin output drivers at the
same time as the Enhanced PWM modes may cause
damage to the application circuit. The Enhanced PWM
modes must be enabled in the proper Output mode and
complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle
is indicated by the TMR2IF or TMR4IF bit of the PIR1
or PIR3 register being set as the second PWM period
begins.
DS39931D-page 260
 2011 Microchip Technology Inc.