PIC18F44J50-I Datasheet, PDF (527/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
TABLE 30-28: MSSPx I²C™ BUS DATA REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100 THIGH Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) —
s
400 kHz mode 2(TOSC)(BRG + 1) —
s
101 TLOW Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) —
s
400 kHz mode 2(TOSC)(BRG + 1) —
s
102 TR
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
—
20 + 0.1 CB
1000
300
ns CB is specified to be
ns ^{from 10 to 400 pF}
103 TF
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
—
20 + 0.1 CB
300 ns CB is specified to be
300 ns ^{from 10 to 400 pF}
90
TSU:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) —
s Only relevant for
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) —
s ^{Repeated Start condition}
91
THD:STA Start Condition 100 kHz mode 2(TOSC)(BRG + 1) —
s After this period, the first
Hold Time
400 kHz mode 2(TOSC)(BRG + 1) —
s ^{clock pulse is generated}
106 THD:DAT Data Input
100 kHz mode
0
—
ns
Hold Time
400 kHz mode
0
0.9 s
107 TSU:DAT Data Input
100 kHz mode
250
Setup Time
400 kHz mode
100
—
ns (Note 1)
—
ns
92
TSU:STO Stop Condition 100 kHz mode 2(TOSC)(BRG + 1) —
s
Setup Time
400 kHz mode 2(TOSC)(BRG + 1) —
s
109 TAA
Output Valid
from Clock
100 kHz mode
400 kHz mode
—
3500 ns
—
1000 ns
110 TBUF Bus Free Time 100 kHz mode
4.7
—
s Time the bus must be
400 kHz mode
1.3
—
s ^{free before a new}
transmission can start
D102 CB
Bus Capacitive Loading
—
400 pF
Note 1: A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but Parameter #107  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCLx signal. If such a device does stretch the LOW period of the SCLx signal, it must output the next data bit
to the SDAx line, Parameter #102 + Parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode), before the
SCLx line is released.
 2011 Microchip Technology Inc.
DS39931D-page 527