PIC18F44J50-I Datasheet, PDF (280/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

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19.4 SPI DMA MODULE
The SPI DMA module contains control logic to allow the
MSSP2 module to perform SPI direct memory access
transfers. This enables the module to quickly transmit
or receive large amounts of data with relatively little
CPU intervention. When the SPI DMA module is used,
MSSP2 can directly read and write to general purpose
SRAM. When the SPI DMA module is not enabled,
MSSP2 functions normally, but without DMA capability.
The SPI DMA module is composed of control logic, a
Destination Receive Address Pointer, a Transmit
Source Address Pointer, an interrupt manager and a
Byte Count register for setting the size of each DMA
transfer. The DMA module may be used with all SPI
Master and Slave modes, and supports both
half-duplex and full-duplex transfers.
19.4.1 I/O PIN CONSIDERATIONS
When enabled, the SPI DMA module uses the MSSP2
module. All SPI related input and output signals,
related to MSSP2, are routed through the Peripheral
Pin Select module. The appropriate initialization proce-
dure, as described in Section 19.4.6 “Using the SPI
DMA Module”, will need to be followed prior to using
the SPI DMA module. The output pins assigned to the
SDO2 and SCK2 functions can optionally be config-
ured as open-drain outputs, such as for level shifting
operations mentioned in the same section.
19.4.2 RAM TO RAM COPY OPERATIONS
Although the SPI DMA module is primarily intended to
be used for SPI communication purposes, the module
can also be used to perform RAM to RAM copy opera-
tions. To do this, configure the module for Full-Duplex
Master mode operation, but assign the SDO2 output
and SDI2 input functions onto the same RPn pin in the
PPS module. Also assign SCK2 out and SCK2 in onto
the same RPn pin (a different pin than used for SDO2
and SDI2). This will allow the module to operate in
Loopback mode, providing RAM copy capability.
19.4.3
IDLE AND SLEEP
CONSIDERATIONS
The SPI DMA module remains fully functional when the
microcontroller is in Idle mode.
During normal Sleep, the SPI DMA module is not func-
tional and should not be used. To avoid corrupting a
transfer, user firmware should be careful to make
certain that pending DMA operations are complete by
polling the DMAEN bit in the DMACON1 register, prior
to putting the microcontroller into Sleep.
In SPI Slave modes, the MSSP2 module is capable of
transmitting and/or receiving one byte of data while in
Sleep mode. This allows the SSP2IF flag in the PIR3
register to be used as a wake-up source. When the
DMAEN bit is cleared, the SPI DMA module is
effectively disabled, and the MSSP2 module functions
normally, but without DMA capabilities. If the DMAEN
bit is clear prior to entering Sleep, it is still possible to
use the SSP2IF as a wake-up source without any data
loss.
Neither MSSP2 nor the SPI DMA module will provide
any functionality in Deep Sleep. Upon exiting from
Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA
related registers will need to be fully reinitialized before
the SPI DMA module can be used again.
19.4.4 REGISTERS
The SPI DMA engine is enabled and controlled by the
following Special Function Registers:
• DMACON1
• TXADDRH
• RXADDRH
• DMABCH
• DMACON2
• TXADDRL
• RXADDRL
• DMABCL
DS39931D-page 280
 2011 Microchip Technology Inc.