PIC18F44J50-I Datasheet, PDF (347/562 Pages) Microchip Technology – 28/44-Pin, Low-Power, High-Performance USB Microcontrollers

PIC18F46J50 FAMILY
21.0 10-BIT ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The Analog-to-Digital (A/D) Converter module has
10 inputs for the 28-pin devices and 13 for the 44-pin
devices. Additionally, two internal channels are available
for sampling the VDDCORE and VBG absolute reference
voltage. This module allows conversion of an analog
input signal to a corresponding 10-bit digital number.
The module has six registers:
• A/D Control Register 0 (ADCON0)
• A/D Control Register 1 (ADCON1)
• A/D Port Configuration Register 2 (ANCON0)
• A/D Port Configuration Register 1 (ANCON1)
• A/D Result Registers (ADRESH and ADRESL)
The ADCON0 register, in Register 21-1, controls the
operation of the A/D module. The ADCON1 register, in
Register 21-2, configures the A/D clock source,
programmed acquisition time and justification.
The ANCON0 and ANCON1 registers, in Register 21-3
and Register 21-4, configure the functions of the port
pins.
REGISTER 21-1: ADCON0: A/D CONTROL REGISTER 0 (ACCESS FC2h)
R/W-0
VCFG1
bit 7
R/W-0
VCFG0
R/W-0
CHS3⁽²⁾
R/W-0
CHS2⁽²⁾
R/W-0
CHS1⁽²⁾
R/W-0
CHS0⁽²⁾
R/W-0
GO/DONE⁽³⁾
R/W-0
ADON
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5-2
bit 1
VCFG1: Voltage Reference Configuration bit (VREF- source)
1 = VREF- (AN2)
0 = AVSS⁽⁴⁾
VCFG0: Voltage Reference Configuration bit (VREF+ source)
1 = VREF+ (AN3)
0 = AVDD⁽⁴⁾
CHS<3:0>: Analog Channel Select bits⁽²⁾
0000 = Channel 00 (AN0)
0001 = Channel 01 (AN1)
0010 = Channel 02 (AN2)
0011 = Channel 03 (AN3)
0100 = Channel 04 (AN4)
0101 = Channel 05 (AN5)⁽¹⁾
0110 = Channel 06 (AN6)⁽¹⁾
0111 = Channel 07 (AN7)⁽¹⁾
1000 = Channel 08 (AN8)
1001 = Channel 09 (AN9)
1010 = Channel 10 (AN10)
1011 = Channel 11 (AN11)
1100 = Channel 12 (AN12)
1101 = (Reserved)
1110 = VDDCORE
1111 = VBG Absolute Reference (~1.2V)⁽³⁾
GO/DONE: A/D Conversion Status bit
When ADON = 1:
1 = A/D conversion in progress
0 = A/D Idle
Note 1:
2:
3:
4:
These channels are not implemented on 28-pin devices.
Performing a conversion on unimplemented channels will return random values.
For best accuracy, the band gap reference circuit should be enabled (ANCON1<7> = 1) at least 10 ms
before performing a conversion on this channel.
On package types that have AVDD and AVSS pins, these pins should be externally connected to VDD and
VSS levels at the circuit board level. Package types that do not have AVDD and AVSS pins, tie AVDD and
AVSS to VDD and VSS internally.
 2011 Microchip Technology Inc.
DS39931D-page 347