MC68HC08XL36 Datasheet, PDF (99/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
CGM Registers
MUL7–MUL4 — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See Circuits on page 85 and
Programming the PLL on page 89.) A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Table 2. VCO Frequency Multiplier (N) Selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
VRS7–VRS4 — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L, which controls the hardware center-of-range frequency
f_vrs. (See Circuits on page 85, Programming the PLL on page 89, and
PLL Control Register on page 94.) VRS7–VRS4 cannot be written
when the PLLON bit in the PLL control register (PCTL) is set. (See
Special Programming Exceptions on page 90.) A value of $0 in the
VCO range select bits disables the PLL and clears the BCS bit in the
PCTL. (See Base Clock Selector Circuit on page 91 and Special
Programming Exceptions on page 90 for more information.) Reset
initializes the bits to $6 to give a default range multiply value of 6.
19-cgm1m_a
MOTOROLA
Clock Generator Module (CGM)
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MC68HC08XL36
99