MC68HC08XL36 Datasheet, PDF (148/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
BRK
BW is for applications that require a return to wait mode after exiting wait
mode for a DMA-generated break interrupt. BW can be read within the
break interrupt routine. The user can modify the return address on the
stack by subtracting 1 from it. The following code is an example.
; This code works if the H register was stacked in the break
; interrupt routine. Execute this code at the end of the break
; interrupt routine.
HIBYTE EQU 5
LOBYTE EQU 6
;
If not BW, do RTI
BRCLR BW,BSR, RETURN
; See if wait mode or stop mode
; was exited by break.
TST LOBYTE,SP
; If RETURNLO is not 0,
BNE DOLO
; then just decrement low byte.
DEC HIBYTE,SP
; Else deal with high byte also.
DOLO DEC LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN PULH
RTI
; Restore H register.
Break Flag Control The break flag control register contains a bit that enables software to
Register
clear status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset: 0
R = Reserved
Figure 6. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
MC68HC08XL36
148
Break Module (BRK)
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Go to: www.freescale.com
8-brk_a
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