MC68HC08XL36 Datasheet, PDF (152/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

MON
Freescale Semiconductor, Inc.
Entering Monitor
Mode
Table 1 shows the pin conditions for entering monitor mode.
Table 1. Monitor Mode Entry
Bus Clock Frequency
V_DD + V_Hi
1
0101
0
C-----G----M----4-X----C-----L---K--- _or C-----G----M----4-V----C-----L---K---
C-----G----M----2-X----C-----L---K---
If the PC3 pin is low upon monitor mode entry, the bus frequency is equal
to the frequency of CGMXCLK divided by two. CGMXCLK is a buffered
version of the clock on the OSC1 pin. If PC3 is high upon monitor mode
entry, the bus frequency is equal to the frequency of CGMXCLK divided
by four. The PLL can be engaged after monitor mode entry to multiply
the bus frequency by programming the CGM. For information on how to
program the PLL, see Clock Generator Module (CGM) on page 81. To
use the PLL, PC3 must be high during monitor mode entry. With the PLL
engaged, the bus frequency is equal to the PLL output, CGMVCLK,
divided by four.
NOTE:
If CGMXCLK divided by two is selected as the bus frequency (PC3 = 0),
the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Enter monitor mode with one of the pin configurations shown in Table 1
by pulling RST low and then high. The rising edge of RST latches
monitor mode. Once monitor mode is latched, the values on the PC0,
PC1, PA0, and PC3 pins can be changed.
NOTE: The PA7 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high.
MC68HC08XL36
152
Monitor ROM (MON)
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4-mon08sp_1p
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