MC68HC08XL36 Datasheet, PDF (67/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

IRQ2 Pin
KB0–KB7 Pins
Interrupt Status
Registers
Freescale Semiconductor, Inc.
Resets and Interrupts
Interrupts
• Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
• Parity error bit (PE) — PE is set when the SCI detects a parity
error in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
A logic 0 on the IRQ2 pin latches an external interrupt request.
A logic 0 on a keyboard interrupt pin latches an external interrupt
request.
The flags in the interrupt status registers identify maskable interrupt
sources. Table 2 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
13-ri24_e
MOTOROLA
Resets and Interrupts
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MC68HC08XL36
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