MC68HC08XL36 Datasheet, PDF (262/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SCI
SCI Status Register 1 SCI status register 1 contains flags to signal the following conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
• Parity error
Address: $0016
Bit 7
6
5
4
3
2
1
Bit 0
Read: SCTE
TC
SCRF IDLE
OR
NF
FE
PE
Write:
Reset: 1
1
0
0
0
0
0
0
= Unimplemented
Figure 14. SCI Status Register 1 (SCS1)
SCTE — SCI Transmitter Empty Bit
This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request or an SCI transmitter DMA service
request. When the SCTIE bit in SCC2 is set and the DMATE bit in
SCC3 is clear, SCTE generates an SCI transmitter CPU interrupt
request. With both the SCTIE and DMATE bits set, SCTE generates
an SCI transmitter DMA service request. In normal operation, clear
the SCTE bit by reading SCS1 with SCTE set and then writing to
SCDR. In DMA transfers, the DMA automatically clears the SCTE bit
when it writes to the SCDR. Reset sets the SCTE bit.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
MC68HC08XL36
262
Serial Communications Interface Module (SCI)
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36-sci_d
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