MC68HC08XL36 Datasheet, PDF (113/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Direct Memory Access Module (DMA)
Functional Description
DMA/CPU Timing
When the DMA transfers data, it takes control of the address bus, data
bus, and R/W line. During DMA transfers, the CPU clock is suspended.
The state of the CPU remains unchanged until the end of the DMA
transfer when the DMA relinquishes control of the buses and R/W line.
Then the CPU resumes operation as though nothing had happened.
Figure 3 and Figure 4 show the timing of DMA transfers.
STATE
1
2
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
3
4
5
6
7
8
9
10
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 3. Single Byte Transfer Timing (Any DMA Bus Bandwidth)
7-dma_b
MOTOROLA
Direct Memory Access Module (DMA)
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MC68HC08XL36
113