MC68HC08XL36 Datasheet, PDF (58/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets and Interrupts
COP Reset
Low-Voltage
Inhibit Reset
Illegal Opcode
Reset
Illegal Address
Reset
A COP reset is an internal reset caused by an overflow of the COP
counter. A COP reset sets the COP bit in the reset status register.
To clear the COP counter and prevent a COP reset, write any value to
the COP control register at location $FFFF.
A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI_tripf voltage. An LVI reset:
• Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to the LVI_tripr voltage.
• Drives the RST pin low for as long as V_DD is below the LVI_tripr
voltage and during the oscillator stabilization delay.
• Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay.
• Releases the CPU to begin the reset vector sequence 64
CGMXCLK cycles after the oscillator stabilization delay.
• Sets the LVI bit in the reset status register.
An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
reset status register.
A mask option enables the STOP instruction. If not enabled by mask
option, the STOP instruction causes an illegal opcode reset.
An illegal address reset is an internal reset caused by an opcode fetch
from an unmapped address. An illegal address reset sets the ILAD bit in
the reset status register.
A data fetch from an unmapped address does not generate a reset.
MC68HC08XL36
58
Resets and Interrupts
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