MC68HC08XL36 Datasheet, PDF (210/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SPI
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK goes back to its
idle level following the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
idle level following the shift of the last data bit. (See Transmission
Formats on page 198.)
NOTE:
When CPHA = 0, a MODF occurs if an idle slave is selected (SS is at
logic 0) and later unselected (SS is at logic 1) even if no SPSCK is sent
to that slave. This happens because SS at logic 0 indicates the start of
the transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, an idle slave can be selected and then later
unselected with no transmission occurring. Therefore, MODF does not
occur since a transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.
NOTE:
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.
MC68HC08XL36
210
Serial Peripheral Interface Module (SPI)
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20-spi_c
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