MC68HC08XL36 Datasheet, PDF (266/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SCI
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates a PE CPU interrupt request if the
PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1 with
PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
SCI Status Register 2
SCI status register 2 contains flags to signal the following conditions:
• Break character detected
• Incoming data
Address: $0017
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BKF
RPF
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 16. SCI Status Register 2 (SCS2)
BKF — Break Flag Bit
This clearable, read-only bit is set when the SCI detects a break
character on the RxD pin. In SCS1, the FE and SCRF bits are also
set. In 9-bit character transmissions, the R8 bit in SCC3 is cleared.
BKF does not generate a CPU interrupt request or a DMA service
request. Clear BKF by reading SCS2 with BKF set and then reading
the SCDR. Once cleared, BKF can become set again only after logic
1s again appear on the RxD pin followed by another break character.
Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
MC68HC08XL36
266
Serial Communications Interface Module (SCI)
For More Information On This Product,
Go to: www.freescale.com
40-sci_d
MOTOROLA