MC68HC08XL36 Datasheet, PDF (260/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SCI
R8 — Received Bit 8
When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.
DMARE — DMA Receive Enable Bit
This read/write bit enables the DMA to service SCI receiver DMA
service requests generated by the SCRF bit. Setting the DMARE bit
disables SCI receiver CPU interrupt requests. Reset clears the
DMARE bit.
1 = DMA enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests disabled)
0 = DMA not enabled to service SCI receiver DMA service requests
generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)
NOTE: To enable the SCRF bit to generate DMA service requests, the SCI
receive interrupt enable bit (SCRIE) must be set.
DMATE — DMA Transfer Enable Bit
This read/write bit enables SCI transmitter empty (SCTE) DMA
service requests. (See SCI Status Register 1 on page 262.) Setting
the DMATE bit disables SCTE CPU interrupt requests. Reset clears
DMATE.
1 = SCTE DMA service requests enabled
SCTE CPU interrupt requests disabled
0 = SCTE DMA service requests disabled
SCTE CPU interrupt requests enabled
MC68HC08XL36
260
Serial Communications Interface Module (SCI)
For More Information On This Product,
Go to: www.freescale.com
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