MC68HC08XL36 Datasheet, PDF (137/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Direct Memory Access Module (DMA)
DMA Registers
The CPU interrupt flag (IFCx) becomes set when the byte count register
equals the block length register.
DTS2–DTS0 — DMA Transfer Source Bits
These read/write bits assign the DMA channels to the eight transfer
source inputs as shown in Table 10.
Table 10. DMA Transfer Source Selection
Transfer Source
TIM Channel 0 Interrupt Request
TIM Channel 1 Interrupt Request
TIM Channel 2 Interrupt Request
TIM Channel 3 Interrupt Request
SPI Receive Interrupt Request
SPI Transmit Interrupt Request
SCI Receive Interrupt Request
SCI Transmit Interrupt Request
DTS2:DTS1:DTS0
000
001
010
011
100
101
110
111
DMA Source
Address Registers
Each DMA channel takes its data from a source base address contained
in a 16-bit source address register. During a block transfer, the DMA
determines successive source addresses by adding to (to increment) or
subtracting from (to decrement) the base address. In static address
transfers, the DMA finds the source address by merely reading the
source address registers. Figure 21 shows the DMA source address
registers. The state of the source address registers after reset is
indeterminate.
31-dma_b
MOTOROLA
Direct Memory Access Module (DMA)
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MC68HC08XL36
137