MC68HC08XL36 Datasheet, PDF (117/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Direct Memory Access Module (DMA)
Functional Description
7. In DMA control register 1 (DC1), make the following selections
(see DMA Control Register 1 on page 129):
a. Enable the DMA channel x by writing to the transfer enable bit,
TECx.
b. Enable or disable DMA channel x to generate CPU interrupts
on transfer completion by writing to the CPU interrupt enable
bit, IECx.
c. Select the DMA bus bandwidth by writing to the bus bandwidth
control bits, BB0 and BB1.
8. To initiate the DMA transfer with software, set the software initiate
bit, SWIx, in DMA control register 2 (DC2). (See DMA Control
Register 2 on page 134.)
Hardware-Initiated
DMA Service
Requests
The following sources can generate DMA service requests:
• Timer interface module TIM) — The TIM can generate the
following DMA service requests:
– TIM channel 0 input capture/output compare
– TIM channel 1 input capture/output compare
– TIM channel 2 input capture/output compare
– TIM channel 3 input capture/output compare
• Serial peripheral interface module (SPI) — The SPI can generate
the following DMA service requests:
– SPI receiver full
– SPI transmitter empty
• Serial communications interface module (SCI) — The SCI can
generate the following DMA service requests:
– SCI receiver full
– SCI transmitter empty
11-dma_b
MOTOROLA
Direct Memory Access Module (DMA)
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MC68HC08XL36
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