MC68HC08XL36 Datasheet, PDF (302/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
IRQ
All of the external interrupt pins are falling-edge-triggered and are
software-configurable to be both falling-edge and low-level-triggered.
The MODE1 bit in the ISCR controls the triggering sensitivity of the IRQ1
pin. The MODE2 bit controls the triggering sensitivity of the IRQ2 pin.
When an interrupt pin is edge-triggered only, the CPU interrupt request
remains latched until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains latched until both of the following occur:
• Vector fetch or software clear
• Return of the interrupt pin to logic 1
The vector fetch or software clear can occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the CPU interrupt request
remains pending. A reset clears the CPU interrupt request and the
MODEx control bit even if the pin stays low.
When set, the IMASK1 and IMASK2 bits in the ISCR mask all external
interrupt requests. A latched CPU interrupt request is not presented to
the interrupt priority logic unless the corresponding IMASK bit is clear.
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all
CPU interrupt requests, including external interrupt requests.
IRQ1 Pin
A logic 0 on the IRQ1 pin can latch a CPU interrupt request. A vector
fetch, software clear, or reset clears the IRQ1 CPU interrupt request.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear the IRQ1 CPU interrupt request:
MC68HC08XL36
302
External Interrupt Module (IRQ)
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4-intirq2_a
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