MC68HC08XL36 Datasheet, PDF (105/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Reaction Time
Calculation
25-cgm1m_a
MOTOROLA
Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
Acquisition/Lock Time Specifications
PLL may become unstable. Also, always choose a capacitor with a tight
tolerance (±20% or better) and low dissipation.
The actual acquisition and lock times can be calculated using the
equations below. These equations yield nominal values under the
following conditions:
• Correct selection of filter capacitor, C_F (See Choosing a Filter
Capacitor on page 104.)
• Room temperature operation
• Negligible external leakage on CGMXFC
• Negligible noise
The K factor in the equations is derived from internal PLL parameters.
K_acq is the K factor when the PLL is configured in acquisition mode, and
K_trk is the K factor when the PLL is configured in tracking mode. (See
Acquisition and Tracking Modes on page 87.)
t_acq
=


V---f--_{rD-d-D-v--A-}
_K----8-a^--_c^--_q^-
t_al
=


V---f--_{rD-d-D-v--A-}


K---4--_t^-_r^-_k^{-}
t_Lock = t_acq + t_al
Note the inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See Manual and
Automatic PLL Bandwidth Modes on page 87.) A certain number of clock
cycles, n_acq, is required to ascertain that the PLL is within the tracking
mode entry tolerance, ∆_trk, before exiting acquisition mode. A certain
Clock Generator Module (CGM)
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MC68HC08XL36
105