MC68HC08XL36 Datasheet, PDF (206/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
SPI
SPI RECEIVE
COMPLETE
BYTE 1
1
SPRF
BYTE 2
3
BYTE 3
4
BYTE 4
6
BYTE 5
OVRF
DMA READ
OF SPDR
2
5
1 BYTE 1 TRANSFERS FROM SHIFT
REGISTER TO DATA REGISTER,
SETTING SPRF BIT.
2 DMA READS BYTE 1, CLEARING SPRF BIT.
3 ^{BYTE 2 TRANSFERS FROM SHIFT}
REGISTER TO DATA REGISTER,
SETTING SPRF BIT.
4 BYTE 3 CAUSES OVERFLOW. BYTE 3 IS LOST.
5 DMA READS BYTE 2, CLEARING SPRF BIT.
6 BYTE 4 IS LOST. NO NEW SPRF DMA SERVICE
REQUESTS AND NO TRANSFERS TO DATA
REGISTER UNTIL OVRF IS CLEARED.
Figure 9. Overflow Condition with DMA Service of SPRF
The overflow service routine may need to disable the DMA and manually
recover since an overflow indicates the loss of data. Loss of data may
prevent the DMA from reaching its byte count.
If an application requires the DMA to bring the MCU out of wait mode,
enable the OVRF bit to generate CPU interrupt requests. An overflow
condition in wait mode can cause the MCU to hang in wait mode
because the DMA cannot reach its byte count. Setting the error interrupt
enable bit (ERRIE) in the SPI status and control register enables the
OVRF bit to bring the MCU out of wait mode.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition. Figure 10 shows how it is possible to
miss an overflow. The first part of Figure 10 shows how it is possible to
read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
MC68HC08XL36
206
Serial Peripheral Interface Module (SPI)
For More Information On This Product,
Go to: www.freescale.com
16-spi_c
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