MC68HC08XL36 Datasheet, PDF (128/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
Freescale Semiconductor, Inc.
DMA Registers
The following registers control and monitor operation of the DMA:
• DMA control register 1 (DC1)
• DMA status and control register (DSC)
• DMA control register 2 (DC2)
DC1, DSC, and DC2 can be written during a DMA transfer without
affecting DMA latency.
The following registers control operation of each of the DMA channels:
• DMA source address registers, high and low (D0SH:D0SL,
D1SH:D1SL, and D2SH:D2SL)
• DMA destination address registers, high and low (D0DH:D0DL,
D1DH:D1DL, and D2DH:D2DL)
• DMA channel x control registers (D0C–D2C)
• DMA channel x byte count registers (D0BC–D2BC)
• DMA channel x block length registers (D0BL–D2BL)
Writing to DxSH:DxSL, DxDH:DxDL, DxC, and DxBL during a transfer
affects DMA latency. A write to a channel x control register during a
transfer has a two-bus cycle latency if the transfer is first suspended by
disabling the channel. Disable the channel by writing a 0 to the TECx bit
in DMA control register 1. Without first suspending the transfer, a write
to a channel x control register during a transfer has a three-bus cycle
latency.
MC68HC08XL36
128
Direct Memory Access Module (DMA)
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Go to: www.freescale.com
22-dma_b
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