MC68HC08XL36 Datasheet, PDF (218/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

SPI
CGND (Clock
Ground)
Freescale Semiconductor, Inc.
The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. (See
Table 4.)
Table 4. SPI Configuration
SPE SPMSTR MODFEN
0
X⁽¹⁾
X
1
0
X
1
1
0
1
1
1
1. X = don’t care
SPI Configuration
Not Enabled
Slave
Master without MODF
Master with MODF
State of SS Logic
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
General-purpose I/O;
SS ignored by SPI
Input-only to SPI
CGND is the ground return for the serial clock pin, SPSCK, and the
ground for the port output buffers. To reduce the ground return path loop
and minimize radio frequency (RF) emissions, connect the ground pin of
the slave to the CGND pin of the master.
I/O Registers
SPI Control
Register
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
The SPI control register does the following:
• Enables SPI module interrupt requests
• Selects CPU interrupt requests or DMA service requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
MC68HC08XL36
218
Serial Peripheral Interface Module (SPI)
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Go to: www.freescale.com
28-spi_c
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