MC68HC08XL36 Datasheet, PDF (303/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
External Interrupt Module (IRQ)
Functional Description
• Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the CPU interrupt
request. Software can generate the interrupt acknowledge signal
by writing a logic 1 to the ACK1 bit in the IRQ status and control
register (ISCR). The ACK1 bit is useful in applications that poll the
IRQ1 pin and require software to clear the IRQ1 CPU interrupt
request. Writing to the ACK1 bit before leaving an interrupt service
routine can also prevent spurious interrupts due to noise. Setting
ACK1 does not affect subsequent transitions on the IRQ1 pin. A
falling edge that occurs after writing to the ACK1 bit latches
another CPU interrupt request. If the IRQ1 mask bit, IMASK1, is
clear, the CPU loads the program counter with the vector address
at locations $FFFA and $FFFB.
• Return of the IRQ1 pin to logic 1 — As long as the IRQ1 pin is at
logic 0, the IRQ1 CPU interrupt request remains latched.
The vector fetch, software clear, or reset and the return of the IRQ1 pin
to logic 1 can occur in any order. A reset clears the CPU interrupt request
and the MODE1 bit, clearing the CPU interrupt request even if the pin
stays low.
If the MODE1 bit is clear, the IRQ1 pin is falling-edge-sensitive only.
With MODE1 clear, a vector fetch or software clear immediately clears
the IRQ1 CPU interrupt request.
The IRQF1 bit in the ISCR register can be used to check for pending
CPU interrupts. The IRQF1 bit is not affected by the IMASK1 bit, which
makes it useful in applications where polling is preferred.
Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.
NOTE:
To avoid spurious CPU interrupts caused by noise, mask CPU interrupt
requests in the interrupt routine when using the level-sensitive interrupt
trigger.
5-intirq2_a
MOTOROLA
External Interrupt Module (IRQ)
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MC68HC08XL36
303