MC68HC08XL36 Datasheet, PDF (168/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
TIM
Register Name
TIM Channel 2 Register Low
(TCH2L)
Read:
Write:
Reset:
TIM Channel 3 Status and Control
Register (TSC3)
Read:
Write:
Reset:
TIM Channel 3 Register High
(TCH3H)
Read:
Write:
Reset:
TIM Channel 3 Register Low
(TCH3L)
Read:
Write:
Reset:
Bit 7
Bit 7
CH3F
0
0
Bit 15
Bit 7
6
6
CH3IE
0
14
6
5
4
3
2
5
4
3
2
Indeterminate after Reset
0
MS3A ELS3B ELS3A
0
0
0
0
13
12
11
10
Indeterminate after Reset
5
4
3
2
Indeterminate after Reset
= Unimplemented
Figure 2. I/O Register Summary (Continued)
1
Bit 0
1
Bit 0
TOV3
0
9
CH3MAX
0
Bit 8
1
Bit 0
Table 2. I/O Register Address Summary
Register TSC TDMA TCNTH TCNTL TMODH TMODL TSC0 TCH0H TCH0L TSC1
Address $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029
Register TCH1H TCH1L TSC2 TCH2H TCH2L TSC3 TCH3H TCH3L
Address $002A $002B $002C $002D $002E $002F $0030 $0031
TIM Counter
Prescaler
Input Capture
The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS2–PS0, in the TIM
status and control register select the TIM clock source.
With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input capture latency can be up to three bus clock
cycles. Input captures can generate TIM CPU interrupt requests or
TIM DMA service requests.
MC68HC08XL36
168
Timer Interface Module (TIM)
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