MC68HC08XL36 Datasheet, PDF (114/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
Freescale Semiconductor, Inc.
Table 2. DMA Byte Transfer Activity
State
Activity
1 DMA service request occurs.
2 DMA arbitrates channel priority.
3 DMA generates internal control signals.
4
DMA calculates source address.
DMA latches source address in temporary register.
DMA drives source address onto address bus.
5
DMA drives R/W line high.
DMA calculates destination address.
DMA latches destination address into temporary register.
6
DMA latches source data into temporary register.
DMA increments byte count register.
DMA drives destination address onto address bus.
DMA drives R/W line low.
7 DMA subtracts byte count register from block length register.
If difference = 0, DMA disables channel by clearing TECx bit.
If difference = 0 and IECx = 1, DMA generates CPU interrupt request.
8 DMA drives source data onto data bus.
9 DMA releases address bus and R/W line to CPU.
10 DMA releases data bus to CPU.
STATE
CGMOUT
ADDRESS
BUS
DATA
BUS
R/W
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
CPU-CONTROLLED BUS CYCLE
DMA-CONTROLLED BUS CYCLE
Figure 4. Single Word Transfer Timing (100% DMA Bus Bandwidth)
MC68HC08XL36
114
Direct Memory Access Module (DMA)
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8-dma_b
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