MC68HC08XL36 Datasheet, PDF (134/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
DMA Control
Register 2
Freescale Semiconductor, Inc.
IFC2–IFC0 — CPU Interrupt Flag Bits
These read/write bits become set when a DMA transfer is complete
or at the end of each transfer loop. IFC2, IFC1, or IFC0 can generate
a CPU interrupt request if the corresponding IECx bit is set in DMA
control register 1. Clear IFC2–IFC0 by reading them and then writing
0s to them. Reset clears the IFC2–IFC0 bits.
1 = DMA transfer complete
0 = DMA transfer not complete
DMA control register 2 can perform two functions:
• Initiate DMA transfers through software
• Simulate DMA service requests for test purposes
Address: $004E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SWI7
Write:
SWI6
SWI5
SWI4
SWI3
SWI2
SWI1
SWI0
Reset: 0
0
0
0
0
0
0
0
Figure 19. DMA Control Register 2 (DC2)
SWI7–SWI0 — Software Initiate Bits
Each of these read/write bits corresponds to one of the eight DMA
transfer sources. (See Table 10 on page 137.) Setting an SWIx bit can
initiate a DMA service request from the selected transfer source.
1 = DMA software transfer initiated
0 = DMA software transfer halted or not initiated
Use the following steps to generate a software-initiated DMA service
request:
1. Enable a channel to perform a transfer by setting its TECx bit.
(See DMA Control Register 1 on page 129.)
MC68HC08XL36
134
Direct Memory Access Module (DMA)
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Go to: www.freescale.com
28-dma_b
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