MC68HC08XL36 Datasheet, PDF (127/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Direct Memory Access Module (DMA)
DMA During Break Interrupts
DMA During Break Interrupts
If the DMA is enabled, clear the DMAP bit in the DMA status and control
register before executing a break interrupt.
If a DMA-generated address matches the contents of the break address
registers, a break interrupt begins at the end of the current CPU
instruction.
If a break interrupt is asserted during the current address cycle and the
DMA is active, the DMA releases the internal address and data buses at
the next address boundary to preserve the current MCU state. During
the break interrupt, the DMA continues to arbitrate DMA channel
priorities. After the break interrupt, the DMA becomes active again and
resumes transferring data according to its highest priority service
request.
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state. (See Break Module (BRK) on
page 141.)
To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a two-step read/write clearing procedure. If software
does the first step on such a bit before the break, the bit cannot change
during the break state as long as BCFE is at logic 0. After the break,
doing the second step clears the status bit.
21-dma_b
MOTOROLA
Direct Memory Access Module (DMA)
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MC68HC08XL36
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