MC68HC08XL36 Datasheet, PDF (140/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
Freescale Semiconductor, Inc.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BL7
BL6
BL5
BL4
BL3
BL2
BL1
BL0
Write:
Reset:
Indeterminate after Reset
Figure 23. DMA Block Length Registers (D0BL–D2BL)
Table 13. DMA Block Length Register Address Summary
Register
Address
D0BL
$0039
D1BL
$0041
D2BL
$0049
DMA Byte Count
Registers
Each read/write DMA byte count register contains the number of bytes
transferred on that channel in the current DMA transfer.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 24. DMA Byte Count Registers (D0BC–D2BC)
Table 14. DMA Byte Count Register Address Summary
Register
Address
D0BC
$003B
D1BC
$0043
D2BC
$004B
Writing to the channel x source address or destination address register
clears the channel x byte count register. The channel x byte count
register also is cleared when its count reaches the value in the channel
x block length register. Reset clears the byte count registers.
MC68HC08XL36
140
Direct Memory Access Module (DMA)
For More Information On This Product,
Go to: www.freescale.com
34-dma_b
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