MC68HC08XL36 Datasheet, PDF (272/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Input/Output Ports
Introduction
Fifty-four bidirectional input-output (I/O) pins form eight parallel ports. All
I/O pins are programmable as inputs or outputs.
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V_DD or
V_SS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Register Name
Read:
Port A Data Register (PORTA) Write:
Reset:
Read:
Port B Data Register (PORTB) Write:
Reset:
Read:
Port C Data Register (PORTC) Write:
Reset:
Read:
Port D Data Register (PORTD) Write:
Reset:
Read:
Data Direction Register A (DDRA) Write:
Reset:
Read:
Data Direction Register B (DDRB) Write:
Reset:
Read:
Data Direction Register C (DDRC) Write:
Reset:
Read:
Data Direction Register D (DDRD) Write:
Reset:
Read:
Port E Data Register (PORTE) Write:
Reset:
Read:
Port F Data Register (PORTF) Write:
Reset:
Bit 7
PA7
PB7
PC7
PD7
DDRA7
0
DDRB7
0
DDRC7
0
DDRD7
0
PE7
0
6
PA6
PB6
PC6
PD6
DDRA6
0
DDRB6
0
DDRC6
0
DDRD6
0
PE6
0
5
PA5
PB5
PC5
PD5
DDRA5
0
DDRB5
0
DDRC5
0
DDRD5
0
PE5
PF5
4
3
PA4
PA3
Unaffected by Reset
PB4
PB3
Unaffected by Reset
PC4
PC3
Unaffected by Reset
PD4
PD3
Unaffected by Reset
DDRA4 DDRA3
0
0
DDRB4 DDRB3
0
0
DDRC4 DDRC3
0
0
DDRD4 DDRD3
0
0
PE4
PE3
Unaffected by Reset
PF4
PF3
Unaffected by Reset
2
PA2
PB2
PC2
PD2
DDRA2
0
DDRB2
0
DDRC2
0
DDRD2
0
PE2
PF2
1
PA1
PB1
PC1
PD1
DDRA1
0
DDRB1
0
DDRC1
0
DDRD1
0
PE1
PF1
Bit 0
PA0
PB0
PC0
PD0
DDRA0
0
DDRB0
0
DDRC0
0
DDRD0
0
PE0
PF0
= Unimplemented
Figure 1. I/O Register Summary
MC68HC08XL36
272
Input/Output Ports
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2-ports_a
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