MC68HC08XL36 Datasheet, PDF (132/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

DMA
Freescale Semiconductor, Inc.
DMAP — DMA Priority Bit
This read/write bit controls the priority of CPU interrupt requests
during DMA transfers. Reset clears the DMAP bit.
1 = CPU interrupt requests inhibited during DMA transfers — When
DMAP is set, a CPU interrupt request is not recognized until
the end of the current DMA transfer. During a block transfer,
the increase in CPU interrupt latency depends on the block
size and on the bus bandwidth bits, BB1 and BB0. (See DMA
Control Register 1 on page 129.)
0 = CPU interrupt requests recognized during DMA transfers —
When DMAP is clear, a CPU interrupt request is recognized
after the transfer of the current byte or word in the current DMA
transfer. The CPU interrupt disables the DMA by clearing the
transfer enable bits, TEC2–TEC0. (See DMA Control Register
1 on page 129.) The DMA can increase CPU interrupt latency
by up to three cycles in a byte transfer or five cycles in a word
transfer.
NOTE:
When DMAP = 0, a CPU interrupt clears the TECx bit if the channel has
a pending DMA transfer. Software must re-enable channel x after each
CPU interrupt by setting the TECx bit.
Table 7 shows the effect of the DMAP bit when the DMA has 100%
of the bus bandwidth (BB1:BB0 = 1:1).
Table 7. DMA Transfer/CPU Interrupt Request Priority Selection
Highest Priority
Lowest Priority
DMAP = 0
CPU Interrupt Requests
DMA Channel 0 Transfer
DMA Channel 1 Transfer
DMA Channel 2 Transfer
DMAP = 1
DMA Channel 0 Transfer
DMA Channel 1 Transfer
DMA Channel 2 Transfer
CPU Interrupt Requests
MC68HC08XL36
132
Direct Memory Access Module (DMA)
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26-dma_b
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