MC68HC08XL36 Datasheet, PDF (47/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
CPU During Break Interrupts
CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See Break Module (BRK) on page 141.) The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted
Instruction Set Summary
Source
Form
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP
AIS #opr
AIX #opr
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP
Table 1. Instruction Set Summary
Operation
Add with Carry
Add without Carry
Add Immediate Value (Signed) to SP
Add Immediate Value (Signed) to H:X
Logical AND
Description
A ← (A) + (M) + (C)
A ← (A) + (M)
SP ← (SP) + (16 « M)
H:X ← (H:X) + (16 « M)
A ← (A) & (M)
Effect on
CCR
VH I NZC
IMM
DIR
EXT
¤
¤
–
¤
¤
¤
IX2
IX1
IX
SP1
SP2
IMM
DIR
EXT
¤
¤
–
¤
¤
¤
IX2
IX1
IX
SP1
SP2
– – – – – – IMM
– – – – – – IMM
IMM
DIR
EXT
0
–
–
¤
¤
–
IX2
IX1
IX
SP1
SP2
A9 ii
2
B9 dd 3
C9 hh ll 4
D9 ee ff 4
E9 ff
3
F9
2
9EE9 ff
4
9ED9 ee ff 5
AB ii
2
BB dd 3
CB hh ll 4
DB ee ff 4
EB ff
3
FB
2
9EEB ff
4
9EDB ee ff 5
A7 ii
2
AF ii
2
A4 ii
2
B4 dd 3
C4 hh ll 4
D4 ee ff 4
E4 ff
3
F4
2
9EE4 ff
4
9ED4 ee ff 5
9-cpu8_a
MOTOROLA
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MC68HC08XL36
47