MC68HC08XL36 Datasheet, PDF (275/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Input/Output Ports
Port A
DDRA7–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA7–DDRA0, configuring all port A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4 shows the port A I/O logic.
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
DDRAx
WRITE PORTA ($0000)
PAx
PAx
READ PORTA ($0000)
Figure 4. Port A I/O Circuit
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit. Table 2 summarizes the operation of
the port A pins.
Table 2. Port A Pin Operation
Data Direction Bit
I/O Pin Mode
0
Input, high-impedance
1
Output
1. Writing affects data register, but does not affect input.
Access to Data Bit
Read
Pin
Write
Latch⁽¹⁾
Latch
Latch
5-ports_a
MOTOROLA
Input/Output Ports
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MC68HC08XL36
275