MC68HC08XL36 Datasheet, PDF (286/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Input/Output Ports
PF5–PF0 — Port F Data Bits
These read/write bits are software programmable. Data direction of
each port F pin is under the control of the corresponding bit in data
direction register F. Reset has no effect on PF5–PF0.
MISO — Master In/Slave Out
The PF3/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled and the PF3/MISO pin is available for general-purpose I/O.
(See Serial Peripheral Interface Module (SPI) on page 191.)
NOTE:
Data direction register F (DDRF) does not affect the data direction of port
F pins that are being used by the SPI module. However, the DDRF bits
always determine whether reading port F returns the states of the
latches or the states of the pins. (See Table 7. Port F Pin Operation.)
MOSI — Master Out/Slave In
The PF2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PPF2/MOSI pin is available for
general-purpose I/O. (See Serial Peripheral Interface Module (SPI)
on page 191.)
SPSCK — SPI Serial Clock
The PF1/SPSCK pin is the serial clock input of the SPI module. When
the SPE bit is clear, the PF1/SPSCK pin is available for
general-purpose I/O.
SS — Slave Select
The PF0/SS pin is the slave select input of the SPI module. When the
SPE bit is clear or when the SPI master bit, SPMSTR, is set, the
PF0/SS pin is available for general-purpose I/O. (See Serial
Peripheral Interface Module (SPI) on page 191.) When the SPI is
enabled, the DDRF0 bit in data direction register F (DDRF) has no
effect on the PF0/SS pin.
MC68HC08XL36
286
Input/Output Ports
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