MC68HC08XL36 Datasheet, PDF (211/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Interrupts
Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests
or DMA service requests:
Table 3. SPI Interrupts
Flag
Conditions for Enabling Interrupt Request
SPTE
Transmitter
Empty
SPI Transmitter CPU Interrupt Request (DMAS = 0, SPTIE = 1,SPE = 1)
SPI Transmitter DMA Service Request (DMAS = 1, SPTIE = 1, SPE = 1)
SPRF
Receiver
Full
SPI Receiver CPU Interrupt Request (DMAS = 0, SPRIE = 1)
SPI Receiver DMA Service Request (DMAS = 1, SPRIE = 1)
OVRF
Overflow
SPI Receiver/Error Interrupt Request (ERRIE = 1)
MODF
Mode Fault
SPI Receiver/Error Interrupt Request (ERRIE = 1)
The DMA select bit (DMAS) controls whether SPTE and SPRF generate
CPU interrupt requests or DMA service requests. When DMAS = 0,
reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. When DMAS = 1, any
read of the receive data register clears the SPRF flag. The clearing
mechanism for the SPTE flag is always just a write to the transmit data
register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests or transmitter DMA
service requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests or receiver DMA service
requests, regardless of the state of the SPE bit. (See Figure 12.)
21-spi_c
MOTOROLA
Serial Peripheral Interface Module (SPI)
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MC68HC08XL36
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