MC68HC08XL36 Datasheet, PDF (205/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Error Conditions
OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. When the DMAS bit is low, the
SPRF, MODF, and OVRF interrupts share the same CPU interrupt
vector. When the DMAS bit is high, SPRF generates a receiver DMA
service request, and MODF and OVRF can generate a receiver/error
CPU interrupt request. (See Figure 12 on page 212.) It is not possible to
enable MODF or OVRF individually to generate a receiver/error CPU
interrupt request. However, leaving MODFEN low prevents MODF from
being set.
When the DMA is enabled to service the SPRF flag, it clears SPRF when
it reads the receive data register. The OVRF bit, however, still requires
the two-step clearing mechanism of reading the flag when it is set and
then reading the receive data register. In this way, the DMA cannot
directly clear the OVRF. However, if the CPU reads the SPI status and
control register with the OVRF bit set, and then the DMA reads the
receive data register, the OVRF bit is cleared.
OVRF interrupt requests to the CPU should be enabled when using the
DMA to service the SPRF if there is any chance that the overflow
condition might occur. (See Figure 9 on page 206.) Even if the DMA
clears the SPRF bit, no new data transfers from the shift register to the
receive data register with the OVRF bit high. This means that no new
SPRF interrupt requests are generated until the CPU clears the OVRF
bit. If the CPU reads the data register to clear the OVRF bit, it could clear
a pending SPRF service request to the DMA.
15-spi_c
MOTOROLA
Serial Peripheral Interface Module (SPI)
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MC68HC08XL36
205