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MC68HC08XL36 Datasheet, PDF (326/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit
Specifications
Freescale Semiconductor, Inc.
Table 6. DC Electrical Characteristics (VDD = 2.0 Vdc ± 10%)(1)
Characteristic
Symbol
Min
Typ(2)
Max
Unit
Output High Voltage
(ILOAD = – 0.5 mA) all ports
VOH
VDD – 0.4
—
—
V
Output Low Voltage
(ILOAD = 0.4 mA) all ports
VOL
—
—
0.2
V
Input High Voltage
All ports, IRQs, RESET, OSC1
VIH
0.7 x VDD
—
VDD
V
Input Low Voltage
All ports, IRQs, RESET, OSC1
VIL
VSS
—
0.2 x VDD V
VDD Supply Current
Run (3)
Wait (4)
Stop (5)
25°C
0° to 85°
—
—
—
6
mA
—
—
3
mA
IDD
—
—
1
µA
—
—
2
µA
I/O Ports Hi-Z Leakage Current
IIL
—
—
± 10
µA
Input Current
IIN
—
—
1
µA
Capacitance
Ports (as Input or Output)
POR ReArm Voltage(6)*
POR Reset Voltage(7)*
COUT
—
CIN
—
VPOR
0
VPORRST
0
—
12
pF
—
8
pF
—
200
mV
700
800
mV
POR Rise Time Ramp Rate(8)
RPOR
0.02
—
—
V/m
s
1. VDD = 2.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25°C only.
3. Run (operating) IDD measured using external square wave clock source (fosc = 8.4 MHz). All inputs 0.2V from
rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2
capacitance linearly affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fosc = 8.4 MHz). All inputs 0.2V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance
linearly affects Wait IDD. Measured with PLL enabled.
5. Stop IDD measured with OSC1 = VSS.
6. Maximum is highest voltage that POR is guaranteed.
7. Maximum is highest voltage that POR is possible.
8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until
minimum VDD is reached.
MC68HC08XL36
326
Specifications
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6-spec_b
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