MC68HC08XL36 Datasheet, PDF (94/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

CGM
Freescale Semiconductor, Inc.
CGM Base Clock
Output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal is used to generate
the MCU clocks. CGMOUT is a 50% duty cycle clock running at twice
the bus frequency. CGMOUT is software programmable to be either the
oscillator output, CGMXCLK, divided by two or the VCO clock,
CGMVCLK, divided by two.
CGM CPU Interrupt CGMINT is the CPU interrupt signal generated by the PLL lock detector.
(CGMINT)
CGM Registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL)
• PLL bandwidth control register (PBWC)
• PLL programming register (PPG)
PLL Control
Register
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
Address: $001C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PLLF
1
1
1
1
PLLIE
PLLON BCS
Write:
Reset: 0
0
1
0
1
1
1
1
= Unimplemented
Figure 4. PLL Control Register (PCTL)
MC68HC08XL36
94
Clock Generator Module (CGM)
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14-cgm1m_a
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