MC68HC08XL36 Datasheet, PDF (237/362 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Serial Communications Interface Module (SCI)
Functional Description
NOTE:
When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.
A good time to toggle the TE bit for a queued idle character is when the
SCTE bit becomes set and just before writing the next byte to the SCDR.
Inversion of
Transmitted
Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
(See SCI Control Register 1 on page 253.)
Transmitter
Interrupts
The following conditions can generate CPU interrupt requests from the
SCI transmitter:
• SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request
or a transmitter DMA service request. Setting the SCI transmit
interrupt enable bit, SCTIE, in SCC2 enables the SCTE bit to
generate transmitter CPU interrupt requests. Setting both the
SCTIE bit and the DMA transfer enable bit, DMATE, in SCC3
enables the SCTE bit to generate transmitter DMA service
requests.
• Transmission complete (TC) — The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.
11-sci_d
MOTOROLA
Serial Communications Interface Module (SCI)
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MC68HC08XL36
237